View FX806ALG_417299.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FX806A AUDIO PROCESSOR
CHIP SELECT POWER SUPPLY C-BUS INTERFACE CALIBRATION INPUT PRIMARY and SECONDARY AUDIO INPUTS ------ Voice. Sub-/Audio Tone. FFSK. etc. SERIAL CLOCK COMMAND DATA MAIN PROCESS OUT SUM OUT MOD. IN
#
MODULATION 1 OUT ATTENUATOR
#
(TX) MIC. IN MIC. & VOGAD AMPS LOW & HIGHPASS FILTERS
VOGAD SENSE
#
VOGAD SENSE
#
VOGAD SENSE
#
#
TRANSMITTER MODULATION DRIVES
# #
GAIN SET
INPUT PROCESS
#
PRE-EMPHASIS LIMITING FILTERING GAIN SETTING
(RX) AUDIO IN
DE-EMPHASIS FILTER
XTAL/CLOCK CLOCK XTAL GENERATOR
BUFFER ATTENUATOR
To EXTERNAL AUDIO PROCESSES
EXTERNAL AUDIO PROCESS IN
Fig.1 FX806A Audio Processor
Brief Description
Intended primarily to operate as the "Audio Terminal" of Radio Systems using the DBS 800 Digitally-integrated Baseband System, the FX806A is a PMR Audio Processor which meets EIA and CEPT audio specifications. Using a unique filter line-up, the FX806A offers lower distortion versus modulation level figures than conventional filter/limiter configurations. The FX806A is a half-duplex device whose signal paths and level-setting elements are dynamically configured and adjusted by digital information sent from the Radio Controller using "C-BUS" hardware and software protocol. Figure 5 shows a complete functional block diagram of the FX806A signal paths which can be viewed as 3 sections: q Input Process Selectable transmit or receive input paths. The transmit path with low-noise input and VOGAD amplifiers and bandpass filtered stages provides good signalto-noise performance at low input levels and minimum distortion for high-drive modulation signals. De-emphasis is software selectable at the Rx Audio Input for FM or PM radio configurations. This initial audio, after in-line gain adjustment, is available for switching to either external audio processes (such as scrambling) or internally to the Main Process stages. q Main Process Conditioning for Input or External Process signals with gain/pre-emphasis, high and lowpass switched capacitor filters and a transmitter deviation limiter. The Main Process Output may be switched to VBIAS. q Summation and Output Drives Main "voice audio" from the Main Process is combined with signalling and data from other DBS 800 facilities, to provide the composite (in and outband) signal for the digitally adjustable Transmitter Modulation Drives. Received audio is level (volume) adjusted for output to loudspeaker circuitry. Signal-level stability and therefore output accuracy, of the FX806A is maintained by a voltage-controlled gain system (VOGAD) with specific gain sensors that are selected automatically by the Internal/External Mode Command. The VOGAD system permits high deviation with low distortion. This is achieved by reducing the path gain (and so reducing the distortion introduced by the Peak Deviation limiter) when the input signal is large. Signal levels can be controlled to provide `dynamiccompensation' for such factors as temperature drift, VCO non-linearity, etc. FX806A audio output stages can be completely disabled or the whole microcircuit placed into a "Powersave" mode, leaving only clock and "C-BUS" circuitry active. The FX806A is a low-power, 5-volt CMOS integrated circuit and is available in 24-pin DIL cerdip and 24-pin/lead plastic SMD packages.
Publication D/806A/3 July 1994
#
#
#
#
ATTENUATOR MODULATION 2 OUT
MAIN PROCESS
MODULATION SUMMING AMP
OUTPUT DRIVES
# indicates logic control
#
LOUDSPEAKER AUDIO
Pin Number Function
FX806A J/LG/LS
1
Xtal: The output of the on-chip clock oscillator. External components are required at this output when a Xtal circuit is employed. See Figure 2, INSET 2.
2
Xtal/clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock should be connected here. See Figure 2, INSET 2. This clock provides timing for on-chip elements, filters etc.
3
Serial Clock: The "C-BUS," serial data loading clock input. This clock, produced by the Controller, is used for transfer timing of Command Data to the Audio Processor. See Timing diagrams and System Support Document.
4
Command Data: The "C-BUS," serial data input from the Controller. Command Data is loaded to this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. The Command/Data instruction is acted upon at the end of loading the whole instruction. Command information is detailed in Tables 1, 2, 3, 4 and 5. See Timing diagrams and System Support Document.
5
Chip Select (CS): The "C-BUS," data loading control function. This input is provided by the Controller. Command Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing diagrams and System Support Document.
6
VOGAD Out: The output of the relevant VOGAD sensor. This output, with external attack and decay setting components, should be connected as in Figures 2 and 3, to the VOGAD In pin.
7
Rx Audio In: The audio input to the FX806A from the radio receiver's demodulator circuits. This input, which requires to be a.c. coupled with capacitor C12, is selected by a Control Command bit.
8
VOGAD In: The gain control signal from the selected VOGAD sensor (VOGAD Out) to the "Input Process" Voltage Controlled Amplifier. VOGAD operation is enabled via a Mode Command (Bit5). Individual sensors, automatically selected, permit gain control from either the Input Process or an external process. External attack and decay setting components should be applied as recommended in Figures 2 and 3.
9
VBIAS: The output of the on-chip analogue circuitry bias system, held internally at VDD/2. This pin should be decoupled to VSS by a capacitor C10, See Figure 2.
10
Mic In (+): The non-inverting input to the microphone Op-Amp. This input requires external components for Op-Amp gain/attenuation setting as shown in Figure 2, INSET 1.
11
Mic In (-): The inverting input to the microphone Op-Amp. This input requires external components for Op-Amp gain/attenuation setting as shown in Figure 2, INSET 1.
12
VSS: Negative supply rail (GND).
2
Pin Number Function
FX806A J/LG/LS
13
Mic Out: The output of the microphone Op-Amp, used with the Mic In (-) input to provide the required gain/attenuation using external components as shown in Figure 2. The external components shown are to assist in the use of this amplifier with either inverting or non-inverting inputs. During Powersave (Volume Command) this output is placed at VSS.
14
Processed Audio In: The input to the device from such external audio processes as Voice Store and Retrieve or Frequency Domain Scrambling. This input, which requires to be a.c. coupled with a capacitor, C13, is selected by a Mode Command bit.
15
External Audio Process: The buffered output of the Input Processing stage. For further external audio processing prior to re-introduction at the Processed Audio In pin.
16
CALibration Input: A unique input, intended to be used for dynamic balancing of the modulator drives and for measuring Deviation Limiter levels. A CUE (beep) input from the FX803 Audio Tone Processor can be entered on this line. This input is selected via a Mode Command bit (11H) and is self-biased.
17
Main Process Out: The output of the Main Process stage. This output is summed with additional system inputs as required (Audio, Sub-Audio Signalling, FFSK - See System Overview) in the on-chip Modulation Summing Amplifier. External components as shown in Figure 2 should be used as required.
18
19
Sum In: The input and output terminals of the on-chip Modulation Summing Amplifier. External components are required for input signals, with gain/attenuation setting as shown in Figure 2. For single-signal, no-gain requirements, Main Process Out may be linked directly to Modulation In. Sum Out:
20
Modulation In: The final, composite modulating signal to VCO (Mod 1) and Reference (Mod 2) Output Drives.
21
Audio Output: The processed audio signal output intended as a received audio (volume) output. Though normally used in the Rx mode, operation in Tx is permitted. The output level of this attenuator is controlled via a Volume Set command. During Powersave this output is placed at VSS.
22
Modulation 1 Drive: The drive to the radio modulator Voltage Controlled Oscillator (VCO), from the composite audio summing stage.
23
Modulation 2 Drive: The drive to the radio modulator Reference Oscillator, from the composite audio summing stage. NOTE: These VCO output attenuators are individually adjustable using the Modulator Levels command. During Powersave these outputs are placed at VSS.
24
VDD: Positive supply rail. A single, stable +5 volt supply is required. Levels and voltages within the Audio Processor are dependant upon this supply.
3
Analogue Application Information
External Components
VDD R6 XTAL SEE INSET 2 XTAL/CLOCK SERIAL CLOCK COMMAND DATA CHIP SELECT C9
1 2 3 4 5 6 7 8 9 10 11 12
VDD
24 23 22 21
MODULATION 2 DRIVE MODULATION 1 DRIVE AUDIO OUT MOD IN SUM OUT SUM IN R8 R7 C11
VSS
EXTERNAL SIGNAL AND DATA INPUTS
VOGAD OUT RX AUDIO IN C12 R
5
FX806A J
20 19 18 17 16 15 14 13
R9
VOGAD IN VBIAS MIC. IN (+) MIC. IN (-) VSS
MAIN PROCESSOUT CALIBRATION IN
R10
EXTERNAL AUDIO PROCESS PROCESSED AUDIO IN MIC. OUT SEE INSET 1 C13
R11
R12 C
8
C10 VSS VSS VBIAS XTAL X1
C5 C MIC. IN (+) C C MIC. IN (-)
2 1 4
1
FX806A J
R4
10
R2
+ -
13
MIC. OUT XTAL/CLOCK
2
C6 C7
11
R1 R3
FX806A J C3
INSET 1
VSS
INSET 2
Fig.2 Recommended External Components
Component R1 = R2 R3 R4 R5 R6 R7 R8 R9 Value 10.0k 10.0k 20.0k 20.0k 10.0k 2.2M 100k 100k 100k
R10 R11 R12 C1 C2 C3 C4 C5 C6
=
100k 100k 2.2M 470nF 470nF 270pF 270pF 0.1F 33pF
C7 = 5 - 65pF C8 1.0F C9 1.0F C10 1.0F C11 22pF C12 100nF C13 10.0nF X13 4.0MHz Tolerance: R = 10%. C = 20%
Notes
To demonstrate the versatility of the Mic. inputs, Input Op-Amp gain/attenuation components for a voltage gain of 6.0dB are shown (INSET 1) in a differential configuration. Components for a single (+ or -) input may be employed. Resistor values R7 to R11 (summation components) are dependant upon application and configuration requirements. Xtal circuit capacitors C6 (CD) and C7 (CG) shown (INSET 2) are recommended in accordance with CML Application Note D/XT/2 December 1991. Circuit drive and drain resistors are incorporated on-chip. Operation of any CML microcircuit without a Xtal or clock input may cause device damage. To minimise damage in the event of a Xtal/drive failure, it is recommended that the power rail (VDD) is fitted with a current limiting device (resistor or fast reaction fuse).
VOGAD Components Calculations - Figures 2 and 3 Provided R5 >>1.0k and R6 = R12 >>R5 Then: Attack Time (TA) = R5 x C8 Decay Time (TD) = R6 x C8 2
4
Analogue Application Information ......
The Gain Control System
EXTERNAL INTEGRATION COMPONENTS
R5 C8
VOGAD IN
R6 R12 VSS
VDD
VOGAD OUT
HI PEAK DETECTOR HI/LO PEAK DETECTOR Tx DRIVES
MIC. OUT MIC. IN
Tx
MIC. IN
VOLTAGE CONTROLLED (VOGAD) AMPLIFIER
MAIN PROCESS
Rx DRIVE
Tx INPUT PROCESS
To EXTERNAL AUDIO PROCESSES PROCESSED AUDIO IN CAL INPUT
Fig.3 "VOGAD" Sensors and Timing Components - (part of Fig.4)
Tx gain control of the FX806A is by 1 of 2 selectable signal peak detectors whose output is fed via external integrating components to the Voltage Controlled Amplifier positioned in the Tx Input Process Path. The integrated level to the VOGAD In pin causes the Voltage Controlled Amplifier gain to be reduced. VOGAD attack and decay calculations are described at the foot of the proceeding page. The FX806A automatically chooses the appropriate peak detector when the signal path is set by a Mode Command. The Hi/Lo Peak Detector is employed when external audio processes are used. The Hi Peak Detector is employed when external audio processes are not used.
25
Limiter Only
20
Output Distortion (%)
15
Internal Path with Pre-emphasis Circuit Elements set to 0dB Input Level for 0dB = 71.0mV p-p Input Frequency = 1.0kHz Output Deviation = 60% = 0dB
"Hi-Peak" VOGAD & Limiter
10
60% Output Deviation 308mVrms
5
0.0 +10.0 0 0.0
0.071
+20.0 0.4 0.6
Input Level (dB) Mic. Input Level (Vp-p)
0.2
Fig.4 Distortion vs Mic. Input Level
Suggested Calibration Methods
To effectively null all internal microcircuit tolerances, the following initial calibration routine is suggested: Tx Calibration : From Mic. In to Modulator Drives Out Disable Peak Detectors (Mode Command). Set Transmitter Drives to 0dB (Mod Levels Set). Pre-emphasis may be employed as required (Control Command). Set Input Level Amp to 0dB (Control Command). (1) Mic. In = 250mVrms at 1kHz; Set Process Gain Amp for output of 1440mV p - p (100% deviation). (2) With Process Gain Amp set as (1); Mic In = 25mVrms at 1kHz, set Input Level Amp for output level of 308 mVrms (60% deviation). Rx Calibration: From Rx Audio In to Audio Output Set Audio Output Drive to 0dB (Volume Set). Leave Process Gain Amp set as In (1) (above). (3) With Rx Audio In level of between 154mVrms and 308mVrms (see Specification page), at 1kHz, set the Input Level Amp for an output level of 308mVrms.
5
PLMR Audio Processor
EXTERNAL INTEGRATION COMPONENTS
Explanatory Block Diagram
VOGAD OUT
EXTERNAL SIGNAL/DATA INPUTS EXTERNAL SIGNAL MIXING
VDD
VOGAD IN
MIC. OUT #M3
0dB
Gain Set By External Components
INPUT SELECT H.P.F.
+VE & -VE PEAKS +VE PEAKS
MIC. IN
HI/LO-PEAK DETECTOR HI-PEAK DETECTOR 0dB to -12.4dB
-24dB to 6dB
Tx #C0 - 3
MAIN PROCESS OUT #V6 VBIAS dB
Tx
SUM IN
SUM OUT
MODULATION IN #D(1) 0-4 MOD 1 dB
0dB
0dB
MIC. IN #M6
ON OFF
MIC. OP-AMP
VOGAD AMP
INPUT L.P.F.
INPUT H.P.F.
VBIAS
+10dB to -4dB
#M0 - 2
-6dB/oct 0dB +3dB to -4dB 0dB
#C4 #M4
Rx
INPUT LEVEL AMP
Rx
Tx
#C6 (ENABLE)
Rx (DEMOD) AUDIO IN
H.P.F.
0dB
TRANSMITTER MODULATOR DRIVES
0dB @ 1kHz
DE-EMPHASIS
DEVIATION LIMITER
PROCESS L.P.F.
PROCESS GAIN AMP
VBIAS
MODULATION SUMMING AMPLIFIER
MOD 2 dB dB
INPUT PROCESS MAIN PROCESS
#M7
0dB to -6.2dB
6
#C5 #M3
+6dB/oct 0dB 0dB
VBIAS
#D(0) 0-4
OUTPUT DRIVES
XTAL/CLOCK
10dB @ 1kHz
CLOCK
PROCESS L.P.F. PRE-EMPHASIS
XTAL
GENERATOR
#C7 (ENABLE)
#V0 - 4
0dB
VSS
BUFFER AMP
dB
dB
AUDIO OUTPUT
SERIAL CLOCK # # # PROCESSED AUDIO IN
VBIAS
VBIAS
0dB to -48.0dB
C-BUS INTERFACE
COMMAND DATA
NOTES
# = Controlling Logic Bit C = Control Command M = Mode Command
CALIBRATION INPUT
D0 = Mod 2 D1 = Mod 1 V = Volume Set 0dB Level = 308mVrms (60% Deviation) .
AND
CONTROL LOGIC
CHIP SELECT EXTERNAL AUDIO PROCESS
Fig.5 PLMR Audio Processor - Facilities
Controlling Protocol
Control of the functions and levels within the FX806A PLMR Audio Processor is by a group of Address/Commands and appended data instructions from the system Controller to set/adjust the functions and elements of the FX806A. The use of these instructions is detailed in the following paragraphs and tables.
Command Assignment
General Reset Control Command Mode Command Mod. Levels Set Volume Set
Address/Command (A/C) Byte Hex Binary
MSB LSB
Command Data
Table
01 10 11 12 13
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 1 1 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 1 1
1 0 1 0 1
+ + + +
1 byte 1 byte 2 bytes 1 byte
2 3 4 5
Table 1 "C-Bus" Address/Commands
In "C-BUS" protocol the FX806A is allocated Address/ Command (A/C) values 10H to 13H. "C-BUS" Command, Mode, Modulation and Volume assignments and data requirements are given in Table 1 and illustrated in Figure 5 (Main Block Diagram). Each instruction consists of an Address/Command (A/C) byte followed by a data instruction formulated from the following tables. Commands and Data are only to be loaded in the group configurations detailed, as the "C-BUS" interface recognises the first byte after Chip Select (logic "0") as an Address/ Command.
Function or Level control data, which is detailed in Tables 2, 3, 4 and 5, is acted upon at the end of the loaded instruction. Upon Power-Up the value of the "bits" in this device will be random (either "0" or "1"). A General Reset Command (01H) will be required. This command is provided to "reset" all devices on the "C-BUS" and has the following effect on the FX806A. Control Address Command Mode Address Command Volume Set Loaded as 00H Loaded as 00H Loaded as 00H
Control Command
Setting
MSB Bit 7 0 1 6 0 1 5 0 1 4 0 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
(Preceded by A/C 10H) Control Bits
Transmitted First Audio Output (Rx) Disabled Enabled
Modulation Drives Disabled Enabled Pre-Emphasis By-Pass Enabled Input Select Rx Audio In Mic. In Input Level Set Input Amp Disabled -4.0dB -3.0dB -2.0dB -1.0dB 0dB 1.0dB 2.0dB 3.0dB 4.0dB 5.0dB 6.0dB 7.0dB 8.0dB 9.0dB 10.0dB
Mode Command
Setting
MSB Bit 7 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1
(Preceded by A/C 11H) Mode Bits
Transmitted First Drive Source Signals Calibration
Deviation Limiter Disabled Enabled VOGAD Disabled Enabled De-Emphasis Enabled By-Passed Signal Select Internal External Process Gain Set -4.0dB -3.0dB -2.0dB 1.0dB 0dB 1.0dB 2.0dB 3.0dB
Table 2 Control Commands
7
Table 3 Mode Commands
Modulator Levels
Setting
Byte 1 MSB 7 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MSB 7 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 6 0 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 5 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
(Preceded by A/C12H) Modulator Drives
First byte for transmission
Must be "0" Mod. 1 Attenuation 12.4dB 12.0dB 11.6dB 11.2dB 10.8dB 10.4dB 10.0dB 9.6dB 9.2dB 8.8dB 8.4dB 8.0dB 7.6dB 7.2dB 6.8dB 6.4dB 6.0dB 5.6dB 5.2dB 4.8dB 4.4dB 4.0dB 3.6dB 3.2dB 2.8dB 2.4dB 2.0dB 1.6dB 1.2dB 0.8dB 0.4dB 0dB
Volume Set
Setting
MSB 7 0 0 5 0 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 0 1
(Preceded by A/C13H) Volume Set
Transmitted First Main Process Out Enabled Biased
Powersave Chip Enabled Powersaved Volume Set Attenuation Off 48.0dB 46.4dB 44.8dB 43.2dB 41.6dB 40.0dB 38.4dB 36.8dB 35.2dB 33.6dB 32.0dB 30.4dB 28.8dB 27.2dB 25.6dB 24.0dB 22.4dB 20.8dB 19.2dB 17.6dB 16.0dB 14.4dB 12.8dB 11.2dB 9.6dB 8.0dB 6.4dB 4.8dB 3.2dB 1.6dB 0dB
Byte 0 6 0 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 5 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Last byte for transmission
Must be "0" Mod. 2 Attenuation 6.2dB 6.0dB 5.8dB 5.6dB 5.4dB 5.2dB 5.0dB 4.8dB 4.6dB 4.4dB 4.2dB 4.0dB 3.8dB 3.6dB 3.4dB 3.2dB 3.0dB 2.8dB 2.6dB 2.4dB 2.2dB 2.0dB 1.8dB 1.6dB 1.4dB 1.2dB 1.0dB 0.8dB 0.6dB 0.4dB 0.2dB 0dB
Table 5 Volume Set
Command Loading Address/Commands and data bytes must be loaded in accordance with the information given in Figure 6 (Timing ). The Powersave function is instigated by bit 5 of the Volume Set Command (Table 5). During Powersave, all internal elements except the Clock Generator and "C-BUS" Interface are off, with the Mic OpAmp and Output Drive stage outputs connected to VSS. Modulator Drives are controlled separately, but the whole two-byte Modulator Drive command must be loaded for each required adjustment. Chip Select must be held at a logic "1" for the period "tCSOFF" between transactions.
Table 4 Modulator Drive Levels
8
Command Loading and Timing
CHIP SELECT
t CSOFF
t CSE
SERIAL CLOCK
t NXT t CK
t NXT
t CSH
COMMAND DATA
7
MSB
6
5
4
3
2
1
0
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ADDRESS/COMMAND BYTE
FIRST DATA BYTE
LAST DATA BYTE
Inter-byte period logic level is not important.
Fig.6 "C-BUS" Timing Information
Parameter
tCSE tCSH tCSOFF tNXT tCK
Min.
2.0 4.0 2.0 4.0 2.0
Typ.
- - - - -
Max.
- - - - -
Unit
s s s s s
Notes (1) (2) (3) (4)
Command Data is transmitted to the peripheral MSB (bit7) first, LSB (bit0) last. Data is clocked into the peripheral on the rising clock edge. Loaded data instructions are acted upon at the end of each individual, loaded byte. To allow for differing Controller serial interface formats, the FX806A will work with either polarity Serial Clock pulses.
Sets the Control, Mode and Volume Commands to 00 H
MSB
GENERAL RESET
LSB
7
MSB
6
5
4
3
2
1
0
TABLE 2
CONTROL COMMAND
LSB
1 DATA BYTE 7 6 5 4 3 2 1 0
TABLE 3
MSB
MODE COMMAND
LSB
1 DATA BYTE 7 6 5 4 3 2 1 0
TABLE 5
MSB
VOLUME SET
LSB
1 DATA BYTE 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TABLE 4
MSB
LSB
2 DATA BYTES - BYTE 1 (loaded first)
BYTE 0 (loaded last)
MODULATOR LEVELS SET
Fig.7 Examples of "Command Data" Configurations
To assist in rapid setting, the "quick-reference" guide below should be used together with Figure 5.
Control
Bit 7 6 5 4 3-0
A/C = 10H
Modulator Levels
Byte 1 Bit 7 - 5 4-0 Byte 2 7-5 4 -0
Audio Out (Rx) Enable Modulator Drive Enable Pre-Emphasis Enable Input Select (Rx/Tx) Input Level Set (-4dB to 10dB) Drive Source Deviation Limiter Enable VOGAD Enable De-Emphasis Enable Signal Select Process Gain Set (-4dB to 3dB)
A/C = 12H
"0" Mod 1 Attenuation (0 to 12.4dB) "0" Mod 2 Attenuation (0 to 6.2dB) "0" Powersave Volume Set Attenuation (0 to 48dB)
Mode
Bit 7 6 5 4 3 2-0
A/C = 11H
Volume Set
Bit 7 - 6 5 4-0
A/C = 13H
Table 6 "Quick-Reference" to Command Allocations
9
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage Input voltage at any pin (ref VSS = 0V) Sink/source current (supply pins) (other pins) Total device dissipation @ TAMB 25C Derating Operating temperature range: FX806A J FX806A LG/LS Storage temperature range: FX806A J FX806A LG/LS -0.3 to 7.0V -0.3 to (VDD + 0.3V) +/- 30mA +/- 20mA 800mW Max. 10mW/C -40C to +85C (cerdip) -40C to +85C (plastic) -55C to +125C (cerdip) -40C to +85C (plastic)
Operating Limits
All device characteristics are measured under the following conditions unless otherwise specified: VDD = 5.0V. TAMB = 25C. Xtal/Clock f0 = 4.0MHz. Audio Level 0dB ref: = 308mVrms @ 1kHz (60% deviation, FM).
Characteristics
Static Values Supply Voltage Supply Current
See Note
Min.
4.5 - - 3.5 - -1.0 -
Typ.
5.0 8.0 0.7 - - - -
Max.
5.5 - - - 1.5 1.0 7.5
Unit
V mA mA V V A pF
(All Elements Enabled) (Maximum Powersave) "C-BUS" Interface Input Logic "1" Input Logic "0" Input Leakage Current (logic "1 or 0") Input Capacitance Dynamic Values Overall Performance Microphone Input Rx Audio In Output Drive Levels For 60% Deviation For 100% Deviation Passband Frequencies Passband Ripple Stopband Attenuation f = 150Hz f = 3400Hz f = 6000Hz f = 8000Hz to 20,000Hz Signal Path Noise Rx Rx Tx Tx Distortion Circuit Elements - Figure 5 Mic Amp or Mod Summation Amp Open Loop Gain Bandwidth Input Impedance Output Impedance (Open Loop) (Closed Loop) De-emphasis Slope Gain (at 1.0kHz) Input Impedance Voltage Controlled Gain Amp Gain (Non-Compressing) (Full Compression) VOGAD In Input Impedance
4, 5 6, 5 5, 7 5, 7, 8 1 2 1, 3
- 154 291 - 297 -2.0 10.0 - 30.0 -
25.0 - 308 1,440 -
- 308 326 - 3000 0.5 - - - - - - - - -
mVrms mVrms mVrms mV p - p Hz dB dB dB dB dB dBp dB dBp dB %
12.0 2.0 36.0 60.0 -60.0 -55.0 -50.0 -45.0 1.0
11 10 11 10
- - - - -
- 20.0 10.0 - - - - - 5 - - -
50.0 - - 6.0 600 -6.0 0 500 6.0 -24.0 10.0
- - - - - - - - - - -
dB kHz M k dB/oct. dB k dB dB M
10
Specification......
Characteristics
VOGAD Peak Detectors Output Impedance - Logic "1" (Compress) - Logic "0" Hi/Lo Peak Detector Thresholds Hi Peak Detector Threshold Input (Low + Highpass) Filter Gain (at 1.0kHz) Input Level Amp Nominal Adjustment Range Error of any Setting Step Size External Audio Buffer Gain Pre-emphasis (Main Process and VOGAD) Slope Gain (at 1.0kHz) Process Highpass Filter Gain (at 1.0kHz) Deviation Limiter Threshold Gain Process Lowpass Filter Gain (at 1.0kHz) Process Gain Amp Nominal Adjustment Range Error of any Setting Step Size Output Impedance Transmitter Modulator Drives Input Impedance Mod.1 Attenuator Nominal Adjustment Range Error of any Setting Step Size Output Impedance Mod.2 Attenuator Nominal Adjustment Range Error of any Setting Step Size Output Impedance Audio Output Attenuator Nominal Adjustment Range Error of any Setting Step Size Output Impedance Miscellaneous Impedances Processed Audio Input Calibration Input External Process Out Rx with De-Emphasis By-Pass
See Note
Min.
- - - - -1.0 -4.0 -1.0 0.75 -0.1 - - -1.0 - -0.5 -1.0 -4.0 -0.5 0.75 - - 0 -1.0 0.2 - 0 -0.6 0.1 - 0 -1.5 - - - - - -
Typ.
1.0 10.0 1,300 650 0
Max.
- - - - 1.0 10.0 1.0 1.25 0.1 - - 1.0 - 0.5 1.0 3.0 0.5 1.25 - - 12.4 1.0 0.6 - 6.2 0.6 0.3 - 48.0 1.5 - - - - - -
Unit
k M mV p - p mV +ve pk dB dB dB dB dB dB/oct. dB dB mV p - p dB dB dB dB dB k dB dB dB dB dB dB dB dB dB k k k
- 1.0 0 6.0 10.0 0 1,300 - 0
- 1.0 600 15.0
- 0.4 600
- 0.2 600
- 1.6 600 500 500 100 25.0
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Between Mic. or Rx inputs to Modulator or Audio outputs. The deviation from the ideal overall response that includes the pre- or de-emphasis slope. Excluding the effect of the pre- or de-emphasis slope. Producing an output of 0dB with the Mic. Op-Amp set to 6dB (as shown in Figure 2) and the Modulator Drives set to 0dB. With Output Drives set to 0dB and the system calibrated, as described in the Application pages. Input level range for 0dB output, by adjustment of the Input Level Amp. It is recommended that these output levels will produce 60% or 100% deviation in the transmitter. With the microphone input level 20dB above the level required to produce 0dB at the Output Drives. Using external components recommended in Figure 2. In a 30kHz bandwidth. dBp = Psophometrically weighted measurement.
11
Package Outlines
The FX806A is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top.
Handling Precautions
The FX806A is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage.
FX806A J 24-pin cerdip DIL
(J4)
FX806A LG 24-pin quad plastic encapsulated bent and cropped (L1)
NOT TO SCALE
NOT TO SCALE
Max. Body Length Max. Body Width
32.03mm 14.81mm
Max. Body Length Max. Body Width
10.25mm 10.25mm
FX806A LS 24-lead plastic leaded chip carrier (L2)
NOT TO SCALE
Ordering Information
FX806A J 24-pin cerdip DIL (J4)
FX806A LG 24-pin encapsulated bent and cropped (L1) FX806A LS 24-lead plastic leaded chip carrier (L2)
Max. Body Length Max. Body Width
10.40mm 10.40mm
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/1 February 2002

▲Up To Search▲

Price & Availability of FX806ALG

	To Download FX806ALG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .